In this article I will talk about the relation between noise (by
Noise here I typically refer to Ground or Power Supply variations) and jitter.
Consider the diagram shown below which shows a variation in
VDD/GND rail. Let us say that the maximum variation (end to end) that occurs in
the PWR or GND rail is X. This variation has a relation with the clock
transitions that occur in the clock buffer used for distribution. Or in other
words the variation X directly translates in the form of jitter in the Clock
Distribution Buffer.
Fig 1. Noise in PWR/GND Rail
Because of above variation in the rail, the transition time for a clock buffer changes which lead not only to more power consumption (How? Can you answer? I will discuss this in some other article but for now we can live with the fact that lower transition rate leads to higher power consumption) but also to jitter. The diagram below shows how such a thing happens:
Because of above variation in the rail, the transition time for a clock buffer changes which lead not only to more power consumption (How? Can you answer? I will discuss this in some other article but for now we can live with the fact that lower transition rate leads to higher power consumption) but also to jitter. The diagram below shows how such a thing happens:
Fig 2. Noise to Jitter Translation in Clock Buffer
The region Y above (which typically in a chip denotes the time difference between the 90% of clock high voltage level and 10% of clock high voltage level and can be put into memory as a rule of thumb) is the region where threshold transition of the logic level happens(region Z). Transition in logic level refers to change in logical “0” to logical “1”. This region is directly dependent on the X. The more the X, the greater will be the value of Y and this will lead to more power consumption. In short Jitter has a relation with Noise which can be described as:
The region Y above (which typically in a chip denotes the time difference between the 90% of clock high voltage level and 10% of clock high voltage level and can be put into memory as a rule of thumb) is the region where threshold transition of the logic level happens(region Z). Transition in logic level refers to change in logical “0” to logical “1”. This region is directly dependent on the X. The more the X, the greater will be the value of Y and this will lead to more power consumption. In short Jitter has a relation with Noise which can be described as:
Y (Jitter) = X(Noise) * dt/dV
where dt/dV is the inverse of slew rate for the clock.
Note that it is X that adds randomness to the jitter
phenomenon.
In short in order to have low jitter it is necessary to
control GND/VDD Bounce. These variation lead to other issues which I will cover in some future topic.
Feedback and comments are welcome.
Upcoming Post : Synchronous and Asynchronous Reset
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